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Senior Analog IC Design Engine

刷新時(shí)間:2023-11-27

北京地太科特電子

20-26萬

北京市 | 大專 | 3-5年

基本信息
工作地點(diǎn):北京市 所屬部門:R&D
職位類別:版圖/電路設(shè)計(jì) 招聘人數(shù):1 人
匯報(bào)對(duì)象:無
職位描述

KNOWLEDGE / SKILLS / EXPERIENCE:
Essential
?Deeply understanding all kinds of analog circuit design and analysis, such as amplifier, comparator, reference resource. Having experience with digital-to-analog converter and analog-to-digital converters.
?Having several times full mixed-signal design flow experience including design, testing and ramp-up.
?Deep understanding signal processing and analysis methods. Familiar using matlab /verilogA to model non-ideal parameters and build correction algorithm.
?Familiar with various EDA tools especially Cadence IC/MMSIM and Mentor Graphics Calibre, simulation method of different circuit performances and physical layout skills.
?Familiar with the characteristics of the CMOS image sensors.

Desirable
?Deeply understanding various instruments, such as oscilloscope, signal generator, to uate the performances of mixed-signal circuit
?Familiar with basic digital circuits and design flow. Be able to convert the correction algorithm to Verilog code.
?Experience with electronic system design will be a plus.
?Experience with image sensor processing circuit design will be a plus.
?Good written and verbal communication skills in English.




Purpose: SiPM Readout IC Feasibility study
Tasks:
TDC(Time-to-digital Converter) study
TDC and Preamplifier system modeling
Requirements:
Major: EE/ME or CS
Degree: MS and above, 211 universities only.
English Level: CET-6 and above
Professional Skills:
1. Familiar with basic analog and digital circuit design.
2. Familiar with Verilog HDL and digital circuit design flow.
3. Basic signal processing knowledge.





崗位要求:
學(xué)歷要求:大專 工作經(jīng)驗(yàn):3-5年
年齡要求:不限 性別要求:不限
語言要求:普通話 專業(yè)要求:不限
企業(yè)信息
公司性質(zhì):其它 公司規(guī)模:100-499人
所屬行業(yè):電子/半導(dǎo)體/集成電路
企業(yè)介紹

http://www.deetee.com

企業(yè)信息

北京地太科特電子

電子/半導(dǎo)體/集成電路

100-499人

其它

北京市朝陽區(qū)望京科技園利澤中園A座4層

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